Daniel Lemire's blog

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How big are your SVE registers ? (AWS Graviton)

5 thoughts on “How big are your SVE registers ? (AWS Graviton)”

  1. -.- says:

    Interesting – svlen_* isn’t documented in the current ACLE, but it seems like it may have been in an earlier version. It seems like current GCC/Clang accept it as well.

    Should probably use the documented svcntb() instead though.

    I think Neoverse V1 is the only ARM processor with 256-bit vectors. Neoverse V2 has reverted to 128-bit vectors.

    1. I agree that svcntb is nicer. Thanks.

      The svlen_* intrinsics are documented in a currently available manual.

      Reference:

      Arm C Language Extensions for SVE
      https://developer.arm.com/documentation/100987/0000/

      Section 6.27.6. LEN: Return the number of elements in a vector

      1. -.- says:

        Weird, I searched that exact document but search didn’t find it for some reason. Oh well, thanks for the correction!

  2. Jorge Bellon says:

    ARM processors with wide vector registers may be difficult to find, but you can find wider vectors in Fugaku’s Fujitsu A64FX CPUs. Their ARM cores also support SVE extensions with 512bit wide SIMD registers:
    https://www.fujitsu.com/global/products/computing/servers/supercomputer/a64fx/

    1. Thanks for the link.